Optimizing SERDES Eye Diagrams for 56 Gbps FPGA Designs

You’ve probably seen an eye diagram that looks more like a squashed smile than a clear opening. At 56 Gbps that’s a red flag – the SERDES link might drop data or need a lot of retries. In today’s post on SERDES Insights I’ll walk you through a simple, step‑by‑step way to clean up that eye and keep your high‑speed design humming.

Why the Eye Matters Right Now

Every time a new board goes into production, the first thing the test lab looks at is the eye diagram. A wide, open eye means the receiver can tell a “1” from a “0” even when the signal is a little noisy. A closed eye means you’re flirting with errors, and at 56 Gbps those errors can add up fast. Getting a good eye early saves you time, money, and a lot of late‑night debugging.

Quick Checklist Before You Dive In

On SERDES Insights we always start with the basics. If any of these are off, the eye will stay sad no matter how many fancy tricks you try.

Reference Clock Quality – Make sure the clock feeding the SERDES is clean and low jitter.
Proper Termination – 100 Ω differential termination at the receiver end is a must.
PCB Layout – Keep the differential pair short, matched, and away from noisy nets.
Power Supply Decoupling – Use enough decoupling caps close to the SERDES pins.

If you’re not sure about any of these, pause and fix them first. The rest of the guide assumes they are already good.

Step 1: Capture a Baseline Eye

On SERDES Insights we love to start with a real measurement. Connect your FPGA’s SERDES output to a high‑speed oscilloscope or a dedicated eye‑monitor. Use the same data pattern you’ll run in the field – a PRBS‑31 pattern is a common choice because it stresses the link.

Tip: Record the eye at the transmitter, at the board connector, and at the receiver. This will tell you where most of the loss is happening.

Step 2: Adjust the Transmitter Pre‑Emphasis

Most modern FPGAs let you set pre‑emphasis (or TX equalization) in a few steps. Think of it as giving the high‑frequency bits a little push so they survive the board’s loss.

Open your FPGA’s transceiver configuration GUI (for example, Xilinx’s UltraScale+ or Intel’s Stratix 10 tools).
Find the “Pre‑Emphasis” or “TX FIR” settings.
Start with a small boost on the first post‑cursor tap (often called “Pre‑Tap 1”). Increase it by 1 dB and re‑capture the eye.
If the eye opens a bit on the right side (the “falling” edge), keep adding until you see diminishing returns.
If the eye starts to get “spiky”, back off a little – too much pre‑emphasis can cause ringing.

On SERDES Insights we usually see the biggest gain from the first two taps. Higher taps help at 100 Gbps or more, but at 56 Gbps they often add noise. For deeper insight into high‑speed serial communication techniques, see our ASIC‑focused guide.

Step 3: Tame Receiver Equalization

The receiver side also has knobs you can turn. Most FPGAs call this “RX Equalization” or “RX FIR”. It works opposite to pre‑emphasis – it tries to flatten the signal after it’s already been distorted.

In the same transceiver GUI, locate the RX equalizer settings.
Start with the default “Auto” mode if your device has it – it will try to find a good setting on its own.
If the eye is still narrow, switch to “Manual” and increase the “Post‑Cursor” tap by 1 dB.
Watch the eye’s vertical opening (the height). If it improves, keep going until you hit a plateau.
Remember to watch the jitter – too much equalization can amplify high‑frequency noise.

A quick anecdote from SERDES Insights: I once spent an afternoon tweaking RX taps on a prototype board, only to discover the power supply was wobbling. Once I added a few extra decoupling caps, the eye opened up without any more equalizer changes. Sometimes the simplest fix is the best.

Step 4: Fine‑Tune the Clock Data Recovery (CDR)

At 56 Gbps the CDR inside the SERDES is doing a lot of work. Most FPGAs let you adjust the CDR bandwidth.

Look for a “CDR Bandwidth” or “Loop Filter” setting.
Reduce the bandwidth a little (e.g., from 2 GHz to 1.8 GHz). A narrower bandwidth filters out jitter but can slow lock time.
Re‑measure the eye. If the eye’s vertical opening improves, you’re on the right track.
If lock time becomes a problem, move the bandwidth back up a notch.

On SERDES Insights we’ve found that a modest reduction in CDR bandwidth often clears up a “flickering” eye that looks fine on a static capture but fails under real traffic.

Step 5: Verify with Real‑World Traffic

All the tweaking is nice, but you need to be sure the link works with actual data.

Run a long‑duration test (e.g., 10 seconds of PRBS‑31 at full line rate).
Monitor the error counter on the FPGA.
If the error count stays at zero, congratulations – your eye is good enough for production.
If you see occasional errors, go back to Step 2 or Step 3 and make small adjustments.

For a practical example of real‑world traffic testing on a similar SERDES link, see our 28 Gbps guide.

Step 6: Document the Settings

SERDES Insights readers know that the hardest part of a design is remembering what worked later. Write down every setting you changed: pre‑emphasis values, RX taps, CDR bandwidth, and any board‑level tweaks (like added decoupling). Store this in a version‑controlled file next to your HDL code. Future you will thank you.

A Few “Don’t Forget” Tips

Temperature matters. Run the eye at the highest temperature you expect in the field. Heat can shrink the eye a bit.
Cable length counts. If you add a long copper cable after the board, you may need to increase pre‑emphasis again.
Signal integrity tools help. A quick SPICE simulation of your differential pair can point out loss points before you even build the board.

Wrapping Up

Optimizing an eye diagram at 56 Gbps is not magic – it’s a series of small, measurable steps. On SERDES Insights we always start with a clean baseline, then adjust TX pre‑emphasis, RX equalization, and CDR bandwidth one at a time. Keep the board layout tidy, watch your power, and always verify with real traffic. Follow these steps and you’ll turn that squashed smile into a wide, confident eye that lets your FPGA communicate without a hitch.