Designing a 28 Gbps SERDES Link with FPGA: Step-by-Step Guide and Common Pitfalls

Why does a 28 Gbps link matter today? Because every new data‑center, every AI accelerator, and every 5G base station is pushing more bits through fewer wires. If your design can’t keep up, the whole system stalls. I’ve spent the last few years wrestling with exactly this speed on a Xilinx UltraScale+ board, and I’ve learned a few things that can save you weeks of debugging.

The Big Picture – What Is a SERDES?

SERDES stands for Serializer/Deserializer. In plain language, it takes a wide, slow parallel bus inside your FPGA and turns it into a narrow, fast serial stream that can travel over a fiber or copper link. The reverse happens on the other side. Think of it as a high‑speed translator that lets your logic talk to the outside world without using a thousand pins. Mastering high‑speed serial communication is essential for reliable operation at 28 Gbps.

At 28 Gbps the timing is tight, the signal integrity is fragile, and the FPGA resources are precious. Below is a practical, step‑by‑step path that I follow for every new link, plus the traps that tend to bite newcomers.

Step 1 – Choose the Right FPGA and Transceiver

H2: Check the transceiver spec sheet

Not every FPGA can do 28 Gbps. Look for a device that lists 28 Gbps or higher line rate in its transceiver table. The UltraScale+ series, for example, offers 32.75 Gbps lanes, giving you a comfortable margin. For a deeper dive, see our step‑by‑step guide for FPGA engineers.

H3: Verify the I/O standard

Your board may use CML (Current Mode Logic) or LVDS (Low‑Voltage Differential Signaling). The transceiver must be configured for the same standard, otherwise you’ll see eye‑diagram collapse right away.

Pitfall: Selecting a device that only supports 25 Gbps and then trying to push 28 Gbps will cause the PLL to lock incorrectly and the link will never train.

Step 2 – Clocking Strategy

H2: Use a clean reference clock

A 28 Gbps link needs a reference clock of at least 156.25 MHz (for a 4× oversampling architecture) or a higher‑speed PLL that can multiply up to the line rate. I always route the reference clock through a dedicated clock buffer and keep it away from noisy digital nets.

H3: Enable jitter cleaning

If your board receives the clock from a noisy source, add a CMOS jitter cleaner (e.g., a Si534x). The cleaner reduces phase noise, which directly improves the eye opening of the serial stream.

Pitfall: Forgetting to enable the PLL’s dynamic re‑configuration mode can lock the PLL to a slightly wrong frequency, leading to intermittent errors that are hard to trace.

Step 3 – Design the Parallel Interface

H2: Pick a sensible data width

At 28 Gbps, a 64‑bit parallel bus at 437.5 MHz is a common choice. The math works out: 64 bits × 437.5 MHz ≈ 28 Gbps. If your logic can’t run that fast, consider a 128‑bit bus at 218.75 MHz – the same line rate, slower clock.

H3: Align your FIFO depth

Insert a small FIFO (First‑In‑First‑Out) buffer between your logic and the SERDES. A depth of 8–16 words absorbs small timing variations and eases the pressure on timing closure.

Pitfall: Using a FIFO that is too shallow will cause overflow or underflow warnings during high‑traffic bursts, and the SERDES will drop bits.

Step 4 – Configure the Transceiver IP

H2: Use the vendor’s wizard, but read the generated code

Both Xilinx and Intel provide a SERDES IP core wizard. Fill in the line rate, data width, and I/O standard, then let the tool generate the HDL. I always open the generated files and check three things:

PLL settings – make sure the multiplier/divider values match your reference clock.
Equalizer configuration – the default may be “auto”; for a 28 Gbps link I usually set a modest pre‑cursor and post‑cursor to compensate for board loss.
Reset sequencing – the transceiver must be held in reset until the PLL locks, then released.

H3: Add a simple loopback test

Before you connect any external optics, enable the internal loopback mode. This routes the serializer output straight back into the deserializer, letting you verify that the core works with a single FPGA.

Pitfall: Skipping the loopback test and going straight to a live link often hides simple configuration errors that become “mystery failures” later.

Step 5 – PCB Layout – The Real Challenge

H2: Keep the differential pair short and matched

A 28 Gbps pair should be no longer than 5 cm on a typical 4‑layer board, and the length mismatch must be under 5 ps (roughly 0.5 mm). Use a controlled‑impedance stack‑up (usually 100 Ω differential) and keep the pair away from large return‑current planes.

H3: Use proper via and connector techniques

If you must use a via, back‑drill it to remove the stub. For connectors, choose a MPO or SFP28 with a rated bandwidth of at least 32 Gbps. The connector’s own loss can eat into your eye diagram budget.

Pitfall: Ignoring the effect of the connector’s insertion loss leads to a closed eye even when the FPGA side looks perfect in simulation.

Step 6 – Verify with an Eye Diagram

H2: Use a high‑speed oscilloscope or a built‑in eye‑monitor

Most modern transceiver IP includes an eye‑monitor register that you can read over JTAG. Pull the data into a Python script and plot it. If you have a scope, connect a high‑bandwidth (≥ 40 GHz) probe to the differential pair and look for a clean eye with at least 70 % opening. For deeper insight, see our article on optimizing eye diagrams.

H3: Adjust equalizer and pre‑emphasis

If the eye is closed on the right side, increase the post‑cursor. If the left side is sagging, raise the pre‑cursor. Small tweaks (1–2 dB steps) often make the difference between a flaky link and a robust one.

Pitfall: Over‑driving the equalizer can create ringing, which looks like a wide eye but actually hides high‑frequency noise that will cause bit errors under temperature drift.

Step 7 – Run a BER Test

H2: Use a PRBS pattern

A Pseudo‑Random Binary Sequence (PRBS) 31 is a good stress test. Run the pattern for at least 10⁹ bits and watch the error counter. If you see any errors, go back to the equalizer settings or check the PCB for unexpected crosstalk.

H3: Log temperature and voltage

High‑speed links are sensitive to temperature and supply voltage. Record these values during the test; a small voltage droop can cause the PLL to wander and produce errors.

Pitfall: Running the test at only room temperature gives a false sense of security. Real systems see a range from -40 °C to +85 °C, so test at the extremes.

Common Pitfalls – A Quick Checklist

Wrong reference clock frequency – double‑check the PLL multiplication.
Mismatched I/O standard – CML vs LVDS must agree on both ends.
Insufficient FIFO depth – leads to overflow/underflow.
Poor PCB routing – length mismatch, impedance discontinuities.
Neglected equalizer tuning – default settings rarely work at 28 Gbps.
Skipping loopback – you lose a cheap sanity check.
Ignoring temperature – test across the full spec range.

Final Thoughts

Designing a 28 Gbps SERDES link is not magic; it is a series of disciplined steps. Pick the right FPGA, give the transceiver a clean clock, match your parallel bus, configure the IP carefully, lay out the board with attention to detail, and verify with eye diagrams and BER tests. When you follow this roadmap, the link will behave predictably, and you’ll avoid the late‑night debugging sessions that I’ve endured more than once.

Happy designing, and may your eyes stay open and your eyes‑diagrams stay wide.