Design a Low‑Jitter 10 MHz Clock Generator for Your FPGA – A Practical Guide

A stable 10 MHz clock is the heartbeat of many FPGA projects. If the pulse wobbles, your logic can miss edges, data can corrupt, and debugging becomes a nightmare. In today’s fast‑moving hobbyist world, getting a clean clock without buying an expensive lab instrument is more doable than ever. Let’s walk through a simple, low‑jitter design that you can build on a breadboard or in a small PCB, and then plug straight into your FPGA.

Why jitter matters

Jitter is just the tiny timing variation from one clock edge to the next. In an FPGA, most timing analysis assumes a fixed period, so any deviation eats into the timing margin you worked hard to meet. A few picoseconds may not matter for a simple UART, but for high‑speed SERDES or precise PWM generation it can cause bit errors or missed deadlines. In short, low jitter = reliable design.

Choosing the right building blocks

Crystal oscillator vs. MEMS resonator

A 10 MHz crystal is cheap, widely available, and offers excellent phase noise performance. MEMS resonators are more rugged and can survive shock, but they usually have a higher phase‑noise floor. For a hobby project where you care more about cost and ease of sourcing, a crystal is the way to go.

Clock buffer

The raw crystal output is a tiny sine wave, not a clean square wave. You’ll need a low‑noise buffer or a dedicated clock driver IC to turn that into a 0‑V to 3.3‑V square wave that the FPGA can accept. Look for parts with low additive jitter (often specified as “jitter contribution” in picoseconds). The Texas Instruments CDCE62005 and Analog Devices AD9500 are popular, but a simple CMOS buffer like the 74HC04 can work if you keep the layout clean.

Simple schematic

Crystal – 10 MHz, 18 pF load caps (check the data sheet for the exact value).
Series resistor – 1 kΩ between the crystal pins and the buffer input. This damps any ringing.
Buffer – a low‑noise CMOS inverter (74LVC1G04 works well).
Power filtering – a 0.1 µF ceramic capacitor right at the buffer VCC pin, plus a 10 µF electrolytic for bulk decoupling.
Output termination – a 33 Ω series resistor before the FPGA pin to match the FPGA’s input impedance and reduce reflections.

That’s it. The whole circuit fits on a small piece of perf‑board.

Layout tips to keep jitter low

Even the best parts can be ruined by a sloppy board. Here are a few habits I’ve picked up over the years:

Keep the crystal close to the buffer – the trace length should be under 5 mm. Any extra length adds inductance and can turn the crystal’s clean sine wave into a noisy mess.
Use a solid ground plane – a continuous copper plane under the crystal and buffer reduces ground impedance, which directly improves jitter.
Separate analog and digital supplies – if you have a separate regulator for the crystal circuit, keep its return path away from the FPGA’s digital ground. This avoids digital switching noise from contaminating the crystal.
Avoid vias on the crystal traces – each via adds parasitic inductance. If you must use a via, keep it short and add a small series resistor (around 10 Ω) to tame any resonance.

Measuring jitter without a scope

You don’t need a 20 GHz oscilloscope to see if your clock is clean. A cheap USB logic analyzer (e.g., Saleae) can capture edge timestamps and let you compute jitter in software. Load the capture into a spreadsheet, calculate the period for each edge, and then find the standard deviation. For a well‑built 10 MHz crystal driver you should see jitter under 50 ps RMS – plenty for most FPGA designs.

Integrating with the FPGA

Most FPGAs have a dedicated clock input pin (often labeled “CLK_IN” or “GCLK”). Connect the buffered output directly to this pin, respecting the voltage levels. If your FPGA runs at 3.3 V, a 3.3 V buffer is fine. For 1.8 V or 2.5 V devices, add a simple level‑shifter or use a buffer that supports the lower voltage.

Inside the FPGA, use a PLL or MMCM to multiply the 10 MHz reference to the frequencies you need. The PLL’s jitter performance is usually better than the input clock, but it can’t fix a badly noisy source. So start with a clean 10 MHz and let the PLL do the heavy lifting.

A quick anecdote

The first time I tried this on a new board, I forgot to add the series resistor between the crystal and the buffer. The result? My FPGA kept locking and unlocking, and the LED blink pattern looked like a strobe light at a disco. After adding a 1 kΩ resistor and moving the crystal a few millimeters closer to the buffer, the lock became rock solid. It reminded me that even a tiny resistor can be the difference between “works” and “mysterious failure”.

Optional upgrades

If you need even lower jitter (sub‑10 ps), consider a temperature‑compensated crystal oscillator (TCXO) or a PLL‑based clock synthesizer. These parts cost more but give you a clean reference that stays stable across temperature swings. For most hobby projects, the simple crystal‑buffer combo is more than enough.

Wrap‑up

Designing a low‑jitter 10 MHz clock generator isn’t rocket science. Pick a good crystal, use a low‑noise buffer, keep the layout tight, and you’ll have a reliable heartbeat for your FPGA. With a little care, you can avoid the dreaded “clock not stable” warnings and focus on the fun part – building the logic that makes your project shine.