Designing a Low‑Noise Sample-and-Hold Amplifier: Step‑by‑Step Guide for Analog Engineers

Ever tried to capture a fast‑changing voltage and found the result looked more like a jittery scribble than a clean snapshot? That’s the noise problem knocking on your bench. In today’s world of mixed‑signal ICs and precision sensors, a low‑noise sample‑and‑hold (S/H) stage can be the difference between a usable data set and a headache‑inducing mess. Let’s walk through a practical design that keeps the noise low, the layout tidy, and the learning curve gentle.

Why Low Noise Matters

Noise is the unwanted background chatter that masks the signal you actually care about. In a sample‑and‑hold circuit the two main noise contributors are the switch and the hold capacitor. When you open the switch, the capacitor is left to “hold” the voltage, but any thermal or flicker noise that got onto the node stays there until the next sample. If that noise is too high, your downstream ADC will see a larger error floor, and you’ll waste precious resolution.

Think of it like trying to take a photo in a dim room with a shaky hand. Even if the camera is great, the blur from the shake (noise) ruins the picture. A clean S/H stage gives the ADC a steady, quiet voltage to digitize.

Basic Building Blocks

Before we dive into the design steps, let’s list the parts that make up a typical low‑noise S/H amplifier:

• Input Buffer – isolates the source from the switch and provides low source impedance.
• Switch – usually a MOSFET; it connects the input to the hold capacitor during the “sample” phase.
• Hold Capacitor – stores the voltage; its value trades off between aperture time and droop.
• Amplifier – a low‑noise op‑amp that buffers the held voltage to the output.
• Control Logic – generates the clock that tells the switch when to open and close.

Each of these can be chosen to keep noise low, but the real art is in how they work together.

The Switch

A good rule of thumb: use a small‑signal MOSFET with low gate charge and low on‑resistance (RDS(on)). The on‑resistance directly adds thermal noise (√(4kTRΔf)). For a 1 kΩ on‑resistance the thermal noise in a 10 kHz bandwidth is already noticeable. Picking a device with RDS(on) under 100 Ω can cut that noise by a factor of three.

When the switch is off, its leakage current can slowly discharge the hold capacitor, causing droop. Choose a MOSFET with low off‑state leakage (sub‑picoamp range) and consider adding a tiny series resistor (10–20 Ω) to dampen charge injection when the switch turns off.

The Hold Capacitor

The capacitor is the heart of the hold phase. Larger capacitance reduces voltage droop (ΔV = Ileak·t / C) but also increases the RC time constant with the switch resistance, which can lengthen the aperture time (the time needed to settle after the switch closes). For low‑noise work, a high‑quality film or C0G/NP0 ceramic capacitor is preferred. They have low dielectric absorption and low loss, which means less noise added during the hold.

A typical value for a modest bandwidth design is 10 nF. If you need faster sampling, you can drop to 1 nF, but be prepared to fight a little more droop.

Step‑by‑Step Design

1. Define Your Specs

Start with the numbers: sampling frequency, input bandwidth, acceptable droop, and noise floor. For example, let’s say we need:

• Sample rate: 100 kS/s
• Input bandwidth: 20 kHz
• Max droop: 1 mV over 10 µs
• Noise floor: < 5 µV rms

These targets will guide component choices.

2. Pick the Input Buffer

A low‑noise, unity‑gain buffer such as the OPA627 or AD797 works well. Their input voltage noise is in the sub‑nanovolt range, and they have enough bandwidth to handle the 20 kHz signal without adding phase lag. Connect the buffer directly to the source; its low output impedance will help the switch settle quickly.

3. Choose the Switch

With a 10 nF hold capacitor, we want the RC time constant (Rswitch·C) to be well under the aperture time. If we aim for a 1 µs aperture, Rswitch should be ≤ 100 Ω. A small‑signal MOSFET like the 2N7002 has an RDS(on) around 5 Ω at 5 V, which is perfect. Add a 10 Ω series resistor to tame charge injection.

4. Size the Hold Capacitor

Using the droop spec: Ileak·t / C ≤ 1 mV. Assuming a worst‑case leakage of 0.5 pA (typical for a good C0G capacitor) and t = 10 µs, we get C ≥ 5 pF. That’s tiny, but we also need enough capacitance for noise filtering. A 10 nF C0G capacitor gives us a comfortable margin and also acts as a low‑pass filter for high‑frequency noise.

5. Select the Output Amplifier

The buffer after the hold capacitor should have low input bias current (to avoid charging the capacitor) and low voltage noise. The same OPA627 can be reused here, set up as a voltage follower. Its input bias current is only a few picoamps, so it won’t disturb the held voltage.

6. Design the Clock

A clean, fast edge clock reduces the time the switch spends in the transition region, where charge injection is highest. Use a CMOS buffer (e.g., 74HC04) driven by a crystal oscillator or a microcontroller PWM with a fast rise time. Add a small series resistor (50 Ω) on the clock line to damp ringing.

7. Layout Tips

• Keep the switch and hold capacitor close together; long traces add parasitic inductance and can pick up noise.
• Ground the analog section with a solid plane, but separate digital clock traces to avoid coupling.
• Place the input buffer right at the source connector, then run a short trace to the switch.
• Use a guard ring around the hold node if you’re working at very low voltages; it reduces leakage paths.

8. Simulate and Verify

Run a SPICE simulation with realistic models for the MOSFET, op‑amps, and capacitor. Look at the noise spectral density at the output and the step response during sampling. Adjust Rswitch or Chold if the aperture time is too long or the droop exceeds the spec.

9. Build and Test

On the bench, use a low‑noise function generator as the input and an oscilloscope with a high‑impedance probe to view the held voltage. Measure the noise with a spectrum analyzer or a high‑resolution ADC. If you see excess noise, check for:

• Poor grounding (common‑mode noise)
• Unintended capacitance on the hold node
• Switch bounce (use a Schmitt trigger on the clock if needed)

10. Iterate

Even after a successful first run, there’s room for improvement. Try a smaller hold capacitor for faster aperture, or a different MOSFET with even lower charge injection. Each tweak teaches you more about the trade‑offs.

A Little Story from My Lab

The first time I built a low‑noise S/H, I was convinced the switch was the culprit because the output looked noisy. I swapped the MOSFET for a JFET, only to discover the real issue was a missing ground stitch under the hold capacitor. Once I added a tiny copper pour, the noise dropped by 40 %. It reminded me that layout is often louder than the parts themselves.

Wrap‑Up

Designing a low‑noise sample‑and‑hold amplifier is a balancing act between switch resistance, capacitor size, and op‑amp choice. By starting with clear specs, picking low‑noise components, and paying close attention to layout, you can build a stage that hands the ADC a clean, steady voltage every time. The next time you need a snapshot of a fast analog signal, give this step‑by‑step recipe a try – you’ll be surprised how quiet the result can be.