Step‑by‑Step Design of a Low‑Pass RF Filter for 5 GHz Applications

Why does a low‑pass filter matter today? Because every modern wireless device—your phone, a Wi‑Fi router, even a satellite link—needs to keep the good signals and throw away the noise. At 5 GHz the wavelengths are short, the board space is precious, and the stakes are high. A well‑designed low‑pass filter can be the difference between a clean link and a dropped call. In this post I’ll walk you through a practical design flow that I use in the RF Filter Lab, from the first spec to a layout that actually works.

Understanding the Specs

What “low‑pass” really means

A low‑pass filter (LPF) lets frequencies below a chosen cutoff pass with little loss, while attenuating everything above that point. In plain language, think of it as a sieve that only lets the small grains (low frequencies) through and blocks the big ones (high frequencies).

Typical 5 GHz requirements

Cutoff frequency (fc): 5 GHz (or a little lower if you need a safety margin)
Insertion loss: < 1 dB in the passband
Return loss: > 15 dB (good match)
Stopband attenuation: > 30 dB at 6 GHz and above
Size: Must fit in a 5 mm × 5 mm footprint on a 0.8 mm FR‑4 board

These numbers come from the data sheets of most 5 GHz transceivers I’ve worked with. Adjust them if your system has tighter constraints.

Choosing the Filter Topology

There are many ways to build an LPF: lumped LC, microstrip, stepped‑impedance, or even a combination. For 5 GHz I usually start with a microstrip coupled‑line topology because it offers a good trade‑off between size and performance on standard PCB material. If you have access to low‑loss substrates like Rogers RO4003, you can push the design even smaller, but FR‑4 works fine for most hobby‑grade projects.

Why not just use a lumped LC?

At 5 GHz the inductors and capacitors you buy off the shelf start to show parasitic resonances. A lumped design can work, but you’ll spend a lot of time tweaking component values and still end up with a bulky board. The microstrip approach uses the board itself as part of the filter, which is more elegant and often cheaper.

Step 1: Define the Characteristic Impedance

Most RF front‑ends are 50 Ω, so we design the filter to match that. The microstrip width that gives 50 Ω depends on the substrate thickness (h) and dielectric constant (εr). For a 0.8 mm FR‑4 board (εr ≈ 4.5) the 50 Ω line is about 1.5 mm wide. I use a quick calculator or the classic TX‑Line formulas to get the exact width.

Step 2: Pick the Order of the Filter

The “order” tells you how many reactive sections the filter has. A 2nd‑order filter (one series inductor and one shunt capacitor) gives about 12 dB/octave roll‑off—good for a gentle slope. For the 30 dB attenuation at 6 GHz we need a steeper slope, so I go with a 4th‑order Chebyshev design. Chebyshev gives a ripple in the passband (usually 0.5 dB) but a much sharper transition, which is exactly what we need.

Step 3: Synthesize the Prototype

Using the standard low‑pass prototype values for a 0.5 dB Chebyshev, the normalized element values (g‑values) are:

g1 = 1.1468
g2 = 1.3712
g3 = 1.3712
g4 = 1.1468

These numbers come from filter tables you can find in any RF textbook. To scale them to our 5 GHz cutoff we use the formulas:

Lk = (Z0 * gk) / (2π * fc) for series inductors
Ck = gk / (Z0 * 2π * fc) for shunt capacitors

Plugging Z0 = 50 Ω and fc = 5 GHz gives us L and C values in the nanohenry and picofarad range. I usually do this math in a spreadsheet; it’s faster than a calculator and you can see the trend at a glance.

Step 4: Convert Lumped Elements to Microstrip Sections

Now the fun part: turning those L and C into physical line lengths. A series inductor becomes a high‑impedance microstrip line (narrow width), while a shunt capacitor becomes a low‑impedance line (wide width). The characteristic impedance of each section (Zk) is derived from the prototype values:

Zk = Z0 / gk for series sections
Zk = Z0 * gk for shunt sections

Using the width‑versus‑impedance formulas for our substrate, I calculate the widths for each section. The lengths are set to a quarter‑wave at the cutoff frequency (λ/4). At 5 GHz, λ in FR‑4 is about 12 mm, so each quarter‑wave is roughly 3 mm. Small adjustments (±0.2 mm) are made to fine‑tune the response.

Step 5: Simulate the Layout

Before cutting any copper, I import the geometry into a 2‑D EM simulator like Keysight ADS or open‑source Sonnet. The simulation shows S‑parameters (S11 = return loss, S21 = insertion loss). If the stopband isn’t deep enough, I tweak the line lengths or add a small series resistor (a few ohms) to improve the match. In my experience, a 0.5 dB ripple spec is easy to meet; the real challenge is keeping the insertion loss under 1 dB, which usually means minimizing bends and keeping the copper smooth.

Step 6: Layout on the PCB

When I move to the PCB editor, I keep a few rules in mind:

Keep the filter away from vias that could introduce unwanted capacitance.
Use 45‑degree traces for bends; they reduce reflection compared to right angles.
Maintain a constant ground plane under the microstrip to preserve the calculated impedance.
Add a guard ring of copper around the filter if you have space; it helps contain the fields.

I like to label each section on the silkscreen (“Z1 high‑Z”, “Z2 low‑Z”) so that anyone looking at the board can follow the design flow. It also makes debugging easier if the measured response deviates from the simulation.

Step 7: Fabricate and Test

Once the board is fabricated, I use a vector network analyzer (VNA) to sweep from 1 GHz to 8 GHz. The key numbers to check:

S21 at 4.5 GHz: should be > ‑0.5 dB (good passband)
S21 at 6 GHz: should be < ‑30 dB (stopband)
S11 across the band: should stay below –15 dB (good match)

If the insertion loss is a bit high, I look for solder bridges or rough edges on the microstrip. A quick re‑flow can often clean that up. In one of my early designs I discovered that a tiny copper burr at a line end added about 0.3 dB loss—nothing dramatic, but it reminded me to inspect the board under a magnifier before testing.

Tips from the RF Filter Lab

Start with a realistic substrate model. FR‑4’s loss tangent rises with frequency; ignore it and you’ll be surprised by extra loss.
Don’t over‑optimize the simulation. Small geometry tweaks in the EM tool can look great on paper but be impossible to manufacture. Keep tolerances in mind.
Document every step. I keep a design notebook (digital or paper) that records the prototype values, scaling equations, and any tweaks. It saves a lot of time when you revisit the design months later.

Designing a low‑pass filter for 5 GHz may sound intimidating, but break it into these bite‑size steps and you’ll see it’s just a series of simple calculations and careful layout work. The satisfaction of seeing a clean –30 dB stopband on your VNA is worth every minute spent tweaking the widths.

Happy filtering!