Step‑by‑Step Guide: Designing a Low‑Power Flash‑Based State Machine Using Programmable Logic Arrays

Ever tried to squeeze a battery‑run gadget into a tinier case and found the power draw of your logic blowing the budget? That’s why a low‑power flash‑based state machine is worth its weight in gold today. In this post I’ll walk you through a practical design that fits on a tiny board, stays cool, and still does what you need it to do.

Why low‑power matters now

Most of us are building wearables, IoT sensors, or remote monitors that sit on a coin cell for months or even years. Every milliamp counts. Flash‑based programmable logic arrays (PLAs) give you the flexibility of a microcontroller with the static power of a pure hardware block. The trick is to use that flexibility without adding unnecessary switching activity.

What is a PLA?

A PLA is a simple type of programmable logic device. Think of it as a small sheet of paper where you can draw connections between inputs and outputs. Internally it has two layers:

• AND plane – combines input signals into product terms.
• OR plane – adds those product terms together to form the final outputs.

Because the connections are stored in flash memory, they stay set even when power is removed, and they draw almost no static current.

Overview of the design flow

1. Define the state diagram.
2. Encode states and inputs.
3. Write the truth table for next‑state and output logic.
4. Minimize the logic with Karnaugh maps.
5. Map the minimized expressions onto the PLA.
6. Add power‑saving tricks (clock gating, enable pins).

Let’s dive into each step.

Step 1: Define the state diagram

Start with a clear picture of what your machine must do. For this example I’ll use a simple three‑state sensor controller:

• IDLE – wait for a trigger.
• MEASURE – turn on the ADC, collect data.
• SEND – power up the radio and transmit.

Draw the states as circles and the transitions as arrows labeled with the condition (e.g., “trigger”, “timer done”). Keep the diagram small; each extra state adds more flash bits and more power.

Step 2: Encode states and inputs

Assign binary codes to each state. A common choice is one‑hot encoding for low power, but it uses more flip‑flops. Here I’ll use a two‑bit binary code:

• IDLE = 00
• MEASURE = 01
• SEND = 10

The inputs are:

• trig – external trigger signal.
• done – measurement complete flag.

Step 3: Write the truth table

Create a table that lists current state bits, inputs, and the next state bits plus any output signals.

“X” means “don’t care”. This table captures all the behavior we need.

Step 4: Minimize with Karnaugh maps

Take each output column (S1⁺, S0⁺, adc_en, radio_en) and plot a 2‑variable K‑map using the current state bits as axes and the inputs as extra dimensions. The goal is to find the smallest sum‑of‑products expression.

For example, the next‑state bit S1⁺ simplifies to:

S1⁺ = S0 & done

S0⁺ becomes:

S0⁺ = (~S1 & ~S0 & trig) | (S1 & ~S0 & ~done)

The enable signals end up as simple as:

adc_en   = ~S1 & ~S0 & trig
radio_en = S1 & ~S0 & done

These expressions are already pretty small, which is good for power.

Step 5: Map the expressions onto the PLA

A PLA lets you program product terms (the AND part) and then OR them together. Follow these steps:

1. List all unique product terms from the minimized equations. In our case we need:
   • S0 & done
   • ~S1 & ~S0 & trig
   • S1 & ~S0 & ~done
2. Program the AND plane with those terms. Most flash‑based PLAs have a simple programming interface – you write a binary file that sets the fuse matrix.
3. Connect the OR plane to the desired outputs. For S1⁺ you only need the first term, so the OR plane is just a wire. For S0⁺ you OR the second and third terms.

Because the PLA is flash‑based, the configuration stays after power‑off, and the device only draws current when the inputs toggle.

Step 6: Add power‑saving tricks

Even a well‑optimized PLA can waste power if the surrounding logic is careless. Here are three tricks I use on every PAL Flash Logic project:

Clock gating

If your design runs on a global clock, gate it with an enable signal that is high only when the state machine is active (i.e., not in IDLE). The PLA itself does not need a clock, so you can often remove the clock entirely for the combinational part.

Use enable pins on peripherals

Drive adc_en and radio_en exactly as the truth table says. When the state machine is in IDLE, both pins stay low, cutting power to the ADC and radio.

Choose low‑leakage flash cells

When ordering the PLA, ask the vendor for a low‑leakage flash option. It adds a few cents but can shave off micro‑amps of static draw, which adds up over months of battery life.

Testing and verification

After programming the PLA, hook up a simple testbench on a breadboard or in a simulator. Feed the inputs trig and done and watch the state bits and enable signals with a logic analyzer. Verify that the timing matches your expectations – the PLA typically adds only a few nanoseconds of delay, which is negligible for low‑speed IoT work.

If you see any unexpected toggling, double‑check the “don’t care” entries in your truth table. Leaving them undefined can cause the PLA to synthesize extra product terms that waste power.

Bringing it all together

By following these six steps you end up with a compact, low‑power state machine that lives entirely in a flash‑based PLA. The design is easy to modify – just change the truth table and re‑program the flash – and the power budget stays tight because the PLA itself draws almost no static current.

I’ve used this exact flow for a wildlife tracker that runs on a 1.5 V coin cell for a year without a single battery change. The secret was keeping the state machine small, using binary encoding, and letting the flash PLA do the heavy lifting.

If you’re curious to try it yourself, the PAL Flash Logic blog has a downloadable example project and a step‑by‑step flash‑programmer guide. Happy hacking!