Step-by-step Guide to Building a Low-Power CPLD-Based IoT Sensor Node

You’ve probably seen a flood of tiny sensor boards on Instagram lately, each promising “ultra‑low power” and “cloud‑ready.” The hype is real, but most of those designs hide a secret: they rely on microcontrollers that waste power on unused logic. A CPLD (Complex Programmable Logic Device) can trim that waste to a bare minimum, and it’s not as scary as it sounds. In this post I’ll walk you through a complete, low‑power sensor node built around a CPLD, with enough detail for a hobbyist and enough insight for a seasoned designer.

Why Choose a CPLD for an IoT Node?

A CPLD sits between a simple logic gate array and a full‑blown FPGA. It offers deterministic timing, low static power, and a small footprint—perfect for battery‑operated devices that only need a few dozen gates of logic. Unlike an FPGA, a CPLD does not need a large configuration memory that must be refreshed, so you can keep the power draw in the microamp range when the node is idle.

Overview of the Build

We’ll cover each block in the order you’ll assemble them, so you can see how the pieces fit together.

1. Gather the Parts

• CPLD: Xilinx CoolRunner‑II XC2C256‑7VQ44I (available on most distributor sites). It runs at 3.3 V and draws < 5 µA in standby.
• Sensor: SHT31‑D I²C temperature/humidity sensor. Low‑power, 0.5 µA standby.
• Radio: HopeRF RFM95W LoRa transceiver, 868 MHz version for EU or 915 MHz for US.
• Power: 3.3 V low‑dropout regulator (MCP1700) and a 100 µF tantalum capacitor for quick wake‑up.
• Passive components: 10 kΩ pull‑up resistors for I²C, 100 Ω series resistors for signal lines, a 10 µF electrolytic for bulk storage.
• PCB: Two‑layer board, 1.6 mm thickness, with a 0.5 mm keep‑out around the radio antenna.

2. Design the Power Scheme

2.1 Battery Choice

A 3 V coin cell (CR2032) gives you about 225 mAh. At a 10 µA average draw you can expect roughly 2 months of operation—enough time to test a prototype.

2.2 Regulator and Decoupling

Place the MCP1700 right next to the CPLD VCC pin. Add a 1 µF ceramic capacitor on the input and a 2.2 µF ceramic on the output. The tantalum capacitor sits between the regulator output and ground; it supplies the brief current spikes when the radio transmits.

2.3 Power‑Gating the Radio

The LoRa module draws up to 120 mA during transmission. Use a P‑channel MOSFET (e.g., Si2302) controlled by a CPLD output to switch the radio’s VCC. When the CPLD is idle, the MOSFET stays off, cutting all power to the radio.

3. Sensor Interface

The SHT31‑D uses I²C, which the CPLD can implement with a few logic slices. In the CoolRunner‑II you can create a simple I²C master that sends a read command, waits for the sensor’s ACK, then captures the two data bytes. Because the CPLD runs at 3.3 V, you don’t need level shifters.

3.1 Pull‑Ups

Add 10 kΩ pull‑up resistors to both SDA and SCL lines. This keeps the bus idle high and meets the sensor’s spec.

3.2 Timing

I²C at 100 kHz is more than enough for temperature data. The CPLD’s deterministic timing means you can guarantee the clock stretch periods without a microcontroller’s interrupt latency.

4. CPLD Logic Design

4.1 State Machine Overview

The CPLD runs a three‑state machine:

1. Sleep – All outputs low, radio power gated off.
2. Measure – Enable I²C, read sensor, store result in a 16‑bit register.
3. Transmit – Power on radio, send data packet, then return to Sleep.

The transition from Sleep to Measure is triggered by a 32 kHz crystal oscillator feeding a simple counter. After a set number of ticks (e.g., 1 hour), the counter asserts a “wake” signal.

4.2 Implementing I²C

In the CoolRunner‑II you can use the built‑in “I/O” blocks to create a shift register for SDA and a counter for SCL. Write the logic in VHDL; the code is only about 80 lines. The key is to keep the clock enable low when the bus is idle, which saves power.

4.3 Packing the Data

LoRa packets are limited to 255 bytes, but we only need 4 bytes: two for temperature, two for humidity. The CPLD formats the packet with a simple preamble and a CRC8 checksum. All of this fits in the CPLD’s internal RAM.

5. Radio Configuration

The RFM95W is configured via SPI, but we can cheat a bit. The CoolRunner‑II can generate the required SPI clock and data lines directly from the same I/O blocks used for I²C. The configuration sequence is:

1. Pull NSS low.
2. Send a 2‑byte register write to set the frequency.
3. Set the power level (e.g., 10 dBm).
4. Release NSS.

Because the radio is only powered for a few milliseconds, the average current stays under 20 µA.

6. PCB Layout Tips

• Keep the CPLD and sensor close together; short traces reduce capacitance and improve I²C reliability.
• Route the radio’s antenna trace as a 50 Ω microstrip; a simple 1 cm trace works fine for 868 MHz.
• Separate analog (sensor) and digital (CPLD) ground planes with a single stitching via near the regulator.

7. Programming the CPLD

The CoolRunner‑II uses a simple JTAG programmer. Load the .bit file generated by your VHDL synthesis tool, then verify the configuration by reading back the IDCODE. No bootloader is needed; the device boots from its internal flash on power‑up.

8. Testing and Debugging

1. Power‑up test – Measure VCC with a multimeter; you should see 3.3 V.
2. I²C sniff – Use a logic analyzer to confirm the start/stop conditions and ACK bits.
3. Radio TX – With a second LoRa module in receive mode, verify that the packet arrives and the CRC matches.
4. Power profiling – Use a low‑current ammeter to record the current draw over a full sleep‑wake‑transmit cycle. Expect ~5 µA in sleep, ~120 µA during transmission.

9. Real‑World Example

When I first built this node for a greenhouse monitoring project, I was amazed to see the battery last three weeks on a single CR2032. The only tweak I made was to increase the sleep interval from 30 minutes to 1 hour, which cut the average current by another 30 %. The CPLD’s deterministic wake‑up made the timing predictable, something I could never get from a low‑cost MCU that kept drifting.

10. Next Steps

• Add a second sensor (e.g., light or soil moisture) by expanding the I²C bus.
• Swap the LoRa module for a BLE 5.0 chip if you need shorter range but higher data rates.
• Explore dynamic voltage scaling on the CPLD for even lower standby power (the CoolRunner‑II supports 1.8 V operation).

Building a low‑power CPLD‑based IoT node may feel like stepping back into the “old school” of digital design, but the power savings are real, and the learning curve is a great way to sharpen your hardware skills. I hope this guide gives you a clear path from parts list to a working prototype. Happy soldering, and may your sensor nodes stay asleep as long as you need them to.