Step‑by‑Step Guide to Building Your First FPGA Project on a UNI‑SIP Board

If you’ve ever stared at a blank FPGA development board and felt the same mix of excitement and dread that I felt the first time I powered up a UNI‑SIP, you’re not alone. The good news is that with a little patience and a clear roadmap, you can turn that blank slate into a blinking LED in an afternoon. This guide walks you through every step, from gathering parts to seeing your design run on the hardware. Let’s get our hands dirty.

What You Need

Before you start, make sure you have the following items on your bench. I keep a small “starter kit” drawer for exactly this purpose, and it saves me a lot of last‑minute trips to the store.

UNI‑SIP board – any of the 7‑series or 10‑series models will do for a first project. I use the UNI‑SIP‑XC7A35T because it’s cheap and has enough I/O for simple experiments.
USB‑JTAG programmer – the official UNI‑SIP programmer works best, but a compatible OpenOCD dongle will also work.
Micro‑USB cable – for power and JTAG communication.
Breadboard and jumper wires – to connect LEDs, switches, or any other peripheral you want to test.
A few LEDs and resistors – 330 Ω resistors are a safe choice for 3.3 V logic.
A PC running Windows, Linux, or macOS – with at least 8 GB of RAM; the toolchain can be a bit memory hungry.
Internet connection – to download the toolchain and reference designs from the UNI‑SIP Prototyping Hub.

Setting Up the Toolchain

Install Vivado (or the free WebPACK)

Xilinx Vivado is the official development environment for UNI‑SIP boards. The free WebPACK edition supports the 7‑series devices, which covers most starter boards. Follow these steps:

Go to the Xilinx download page and grab the latest WebPACK installer.
Run the installer and select “Custom Installation”. Uncheck everything you don’t need – I usually leave out the IP catalog for now.
After installation, add the Vivado bin directory to your system PATH. On Windows, this is something like C:\Xilinx\Vivado\2023.1\bin. On Linux/macOS, add export PATH=$PATH:/opt/Xilinx/Vivado/2023.1/bin to your .bashrc.

Install the UNI‑SIP Board Support Package

The board support package (BSP) tells Vivado where the pins are and how to program the device.

Clone the BSP repository from the UNI‑SIP Prototyping Hub: git clone https://github.com/logzly/unisiphub-bsp.git.
Copy the unisip_xc7a35t folder into Vivado’s boards directory (<vivado_install>/data/boards/board_files).
Restart Vivado – the new board should appear in the “Boards” list when you create a new project.

Your First Design: Blinking an LED

A blinking LED is the “Hello, World!” of FPGA design. It teaches you how to write HDL, synthesize, implement, and program – all in one go.

Create a New Project

Open Vivado and click Create New Project.
Name it blink_led and choose a location you can easily find.
Select RTL Project and tick “Do not specify sources at this time”. We’ll add them later.
In the Default Part screen, choose Boards and pick UNI‑SIP‑XC7A35T.
Finish the wizard.

Write the HDL Code

I prefer Verilog for its simplicity. Create a new file blink.v with the following content:

module blink (
    input  wire clk,
    output reg  led
);
    // 25 MHz clock divided down to about 1 Hz
    reg [24:0] counter = 0;

    always @(posedge clk) begin
        counter <= counter + 1;
        if (counter == 25_000_000) begin
            led <= ~led;
            counter <= 0;
        end
    end
endmodule

A quick note on the numbers: the UNI‑SIP board runs at 25 MHz by default, so counting to 25 million gives roughly a one‑second period. Adjust the constant if you use a different clock.

Add this file to the project (right‑click Sources → Add Sources → Add or Create Design Files).

Constrain the Design

Constraints tell the FPGA which pins to use. Create a file blink.xdc:

# Clock input
set_property PACKAGE_PIN E3 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports clk]

# LED output
set_property PACKAGE_PIN G13 [get_ports led]
set_property IOSTANDARD LVCMOS33 [get_ports led]

The pin numbers match the silk screen on the UNI‑SIP board; you can verify them in the board’s schematic on the hub.

Add the XDC file to the project (right‑click Constraints → Add Sources).

Run Synthesis and Implementation

Click Run Synthesis, wait for it to finish, then Run Implementation. If everything is wired correctly, Vivado will report “Timing Constraints Met”. No errors? Great – you’re ready to program.

Programming the Board

Connect the Hardware

Plug the USB‑JTAG programmer into your PC.
Connect the programmer’s JTAG cable to the UNI‑SIP’s JTAG header (the four‑pin connector near the power jack).
Power the board via the micro‑USB cable – the LED on the board should light up, indicating it’s receiving power.

Export the Bitstream

In Vivado, click Generate Bitstream. This creates a .bit file that contains the configuration data for the FPGA.

Load the Bitstream

Open the Hardware Manager (Flow → Open Hardware Manager → Open Target → Auto Connect). Once the board is detected:

Click Program Device.
Browse to the generated .bit file.
Click Program.

If the programming succeeds, the board’s LED should start blinking at a steady one‑second rate. If not, double‑check the JTAG connections and make sure the board is powered.

Testing and Debugging

Even a simple design can hide subtle bugs. Here are a few tricks I use:

LED polarity – Some boards label the LED pin opposite to the actual silicon. If the LED stays off, try swapping the LED’s anode and cathode.
Clock source – If you changed the clock pin in the XDC file, make sure the external oscillator (if any) matches the frequency you assumed.
Signal integrity – Long jumper wires can introduce noise. Keep connections short, especially for the clock line.

If the LED blinks too fast or too slow, adjust the counter limit in the Verilog code. A quick way to see the actual frequency is to attach a logic analyzer (or even a cheap USB oscilloscope) to the LED pin and measure the period.

Next Steps

Now that you have a working blink project, you can start adding more features:

Add a button to pause or reset the blink.
Drive a 7‑segment display to show a binary count.
Experiment with PWM to dim an LED.

All of these examples are available on the UNI‑SIP Prototyping Hub, complete with source code and wiring diagrams. Dive in, tweak the designs, and make them your own. The best way to learn FPGA design is by building, breaking, and rebuilding.

Happy prototyping!