--- title: Designing a Low-Noise Sample-and-Hold Amplifier: Step-by-Step Guide for Precise Analog Capture siteUrl: https://logzly.com/signalcapturelab author: signalcapturelab (Signal Capture Lab) date: 2026-06-19T22:04:28.710365 tags: [lownoise, sampleandhold, analogdesign] url: https://logzly.com/signalcapturelab/designing-a-low-noise-sample-and-hold-amplifier-step-by-step-guide-for-precise-analog-capture --- Ever tried to grab a fleeting ripple on a pond with a bucket? That’s what a sample‑and‑hold (S/H) circuit does to an [analog signal](/signalcapturelab/mastering-analog-signal-conditioning-practical-circuit-techniques-for-precise-data-acquisition) – it snatches a momentary voltage and keeps it steady long enough for the rest of the system to read it. In today’s world of high‑speed ADCs and mixed‑signal chips, a noisy S/H can ruin everything from audio quality to sensor accuracy. Let’s walk through a practical, low‑noise design that you can build on a bench or embed in a PCB, without needing a PhD in cryogenics. ## Why Noise Matters Noise is the unwanted jitter that blurs the picture of your signal. In a sample‑and‑hold, two main noise sources dominate: 1. **Thermal (Johnson) noise** from resistors and the input stage. 2. **Switching noise** generated when the sampling switch opens and closes. If either of these is too high, the voltage you think you captured will be a fuzzy version of the real thing. Designing a [low‑noise sample‑and‑hold amplifier](/signalcapturelab/how-to-design-a-lownoise-sampleandhold-amplifier-for-precision-data-acquisition) is essential for precision analog front‑ends. For audio, that means hiss; for a sensor, it means a wrong reading. Keeping noise low is not a luxury – it’s a requirement for any precision analog front‑end. ## What Is a Sample‑and‑Hold, Plain and Simple? A sample‑and‑hold circuit consists of three basic blocks: * **Input buffer** – isolates the source and provides low output impedance. * **Sampling switch** – usually a MOSFET that connects the buffer to a storage capacitor for a brief instant. * **Hold capacitor** – stores the voltage while the switch is off, presenting a stable voltage to the next stage. Think of the buffer as a polite friend who never lets strangers touch your coffee mug, the switch as a quick hand that lifts the mug for a second, and the capacitor as the mug itself that keeps the coffee warm while you walk away. ## Step 1: Choose the Right Buffer The buffer sets the noise floor and the bandwidth. For low‑noise work, a precision op‑amp with low input voltage noise (under 5 nV/√Hz) and low bias current is ideal. In my lab I often reach for the **OPA827** – it’s a bit pricey but its 4 nV/√Hz noise and 0.1 µA bias current make the rest of the design easier. **Tips:** * Keep the feedback network simple – a single resistor from output to negative input and a capacitor for stability. * Use a gain of 1 (voltage follower) unless you need to scale the signal. Unity gain avoids extra noise from gain stages. ## Step 2: Pick the Sampling Switch A MOSFET works best because its on‑resistance can be very low, reducing charge injection. Look for a device with: * Low **RDS(on)** (under 1 Ω) – less voltage drop while sampling. * Small **gate charge** – faster turn‑on/off, less switching noise. * Low **parasitic capacitance** – preserves bandwidth. The **BSS138** is a handy little N‑channel part that meets these criteria for most low‑frequency applications. For higher speed, consider a **SiGe** switch, but the price and layout become more critical. ## Step 3: Size the Hold Capacitor The hold capacitor determines two things: 1. **Hold error** – how much the voltage droops while the switch is off. 2. **kT/C noise** – thermal noise that appears as a voltage variance, given by √(kT/C). A larger capacitor reduces kT/C noise but slows the circuit because it takes longer to charge. A good compromise for many lab‑scale projects is **10 pF to 100 pF** of **C0G/NP0** ceramic. These have very low dielectric loss, meaning they add almost no extra noise. **Quick calculation:** At room temperature (kT ≈ 4 µeV), a 10 pF capacitor yields about 0.65 µV rms of kT/C noise – negligible for most audio or sensor work. ## Step 4: Add a Small Bleed Resistor When the switch opens, the capacitor can retain charge for a long time, which is fine for a hold period but can cause a “ghost” when the next sample arrives. A high‑value resistor (1 MΩ to 10 MΩ) across the capacitor gently discharges it between samples, preventing buildup. The resistor adds a tiny amount of thermal noise, but at 1 MΩ it’s only about 4 nV/√Hz – still well below the op‑amp’s own noise. ## Step 5: Clock the Switch Cleanly The timing signal that drives the MOSFET gate should have a fast edge and low jitter. Use a **CMOS buffer** (like the **74HC04**) to sharpen the edges and isolate the digital source from the analog ground. Add a small series resistor (50 Ω) between the buffer output and the MOSFET gate to damp ringing caused by gate capacitance. ## Step 6: Layout – The Unsung Hero Even the best parts can misbehave on a messy board. Follow these layout rules: * Keep the buffer and switch close together – short traces reduce parasitic inductance. * Route the hold capacitor’s leads directly to the switch node; avoid long loops. * Separate analog and digital grounds, but connect them at a single point near the power supply. * Use a solid ground plane under the analog section to provide a low‑impedance return path. For a comprehensive [step‑by‑step layout guide](/signalcapturelab/designing-a-lownoise-sample-and-hold-amplifier-stepbystep-guide-for-analog-engineers), see our dedicated article. A quick anecdote: In my first S/H prototype I placed the hold capacitor near a switching regulator. The regulator’s high‑frequency ripple showed up as a nasty ripple on the held voltage. Moving the capacitor away and adding a small guard ring solved it in minutes. ## Step 7: Verify Performance Once built, measure two key parameters: 1. **Noise spectral density** – use a spectrum analyzer or a low‑noise ADC to see the noise floor. You should see a flat line near the op‑amp’s spec, with a small bump at the switching frequency. 2. **Hold error vs. time** – feed a steady DC voltage, sample, then watch the voltage decay. The slope gives you the effective leakage; adjust the bleed resistor if needed. If the noise is higher than expected, double‑check the power supply decoupling. A 0.1 µF ceramic close to the op‑amp’s supply pins can shave off a lot of high‑frequency noise. ## Putting It All Together Here’s a concise checklist for a low‑noise S/H: | Item | Recommended Choice | |------|--------------------| | Buffer op‑amp | OPA827 (or similar low‑noise) | | Switch MOSFET | BSS138 (or low‑RDS(on) N‑MOS) | | Hold capacitor | 10‑100 pF C0G/NP0 | | Bleed resistor | 1 MΩ (optional) | | Gate driver | 74HC04 + 50 Ω series | | Layout tip | Keep analog traces short, separate grounds | With these parts and a tidy layout, you’ll have a sample‑and‑hold that captures analog signals cleanly, holds them steady, and lets your downstream ADC or processor work with confidence.