--- title: Designing a 28 Gbps SERDES Link: Step‑by‑Step Guide for FPGA Engineers siteUrl: https://logzly.com/serdesinsights author: serdesinsights (SERDES Insights) date: 2026-06-15T20:34:35.323837 tags: [serdes, fpga, highspeed] url: https://logzly.com/serdesinsights/designing-a-28-gbps-serdes-link-stepbystep-guide-for-fpga-engineers --- **Disclosure: We are reader supported, and earn affiliate commissions when you buy through us.** When the next generation of data‑center cards arrives, the first thing you’ll hear is “we need 28 Gbps lanes, and we need them now.” In a world where a single video stream can out‑run a whole hard‑drive, mastering a 28 Gbps SERDES link is no longer a nice‑to‑have skill – it’s a survival skill for any FPGA engineer. Below is the practical, down‑to‑earth path I follow every time I take a new design from concept to silicon. I’ve stripped away the academic fluff and kept only the steps that actually move a project forward. Feel free to copy, adapt, or even break a rule or two – just remember to test, test, and test again. For a comprehensive walkthrough, see the [step‑by‑step SERDES design guide](/serdesinsights/designing-a-28-gbps-serdes-link-stepbystep-guide-for-fpga-engineers). ## 1. Know Your Target FPGA and Its SERDES Capabilities ### 1.1 Check the datasheet, not the marketing brochure The first thing I do is open the FPGA’s official data sheet and locate the “SERDES” or “High‑Speed Transceiver” section. Look for: * Maximum line rate (often listed as “28 Gbps” or “56 Gb/s DDR”) * Supported encoding (8b/10b, 64b/66b, etc.) * Number of available lanes and their grouping (e.g., 4 × 7 Gbps or 2 × 14 Gbps) * Clocking options – does the part need an external reference, or can it use a PLL inside the chip? If the part lists a “28 Gbps line rate” but only for a 64b/66b encoding, you’ll need to budget extra overhead for the 3% encoding penalty. ### 1.2 Pick the right I/O standard Most 28 Gbps designs use either CML (Current Mode Logic) or LVDS (Low‑Voltage Differential Signaling) on the board. CML gives you lower jitter but needs careful biasing; LVDS is easier on power but can be more sensitive to noise. My personal favorite for a clean lab prototype is CML, because the eye diagram looks nicer and the margin is easier to see. ## 2. Clock Architecture – The Heartbeat of a SERDES ### 2.1 Choose a reference clock A stable 156.25 MHz reference is the de‑facto standard for 28 Gbps links that use 64b/66b encoding. The PLL inside the FPGA multiplies this up to the required serial clock (28 Gbps / 66 bits ≈ 425.6 MHz for the parallel domain). If you have a clean external clock, feed it directly; otherwise, use a low‑jitter crystal oscillator and a clean‑up PLL on the board. ### 2.2 Manage jitter Jitter is the silent killer of high‑speed links. I always add a simple RC low‑pass filter on the reference clock line and keep the trace length under 5 mm. In the FPGA, enable the “jitter‑cleaner” feature of the transceiver PLL if it’s available – it can shave off a few picoseconds of phase noise. ## 3. Physical Design – PCB Layout Tips ### 3.1 Keep the differential pair tight For 28 Gbps, the pair spacing should be about 0.15 mm ([6 mil](https://www.amazon.com/s?k=6+mil&tag=organizationtip101-20)) with a length mismatch under 5 mil (0.13 mm). Use a controlled‑impedance stack‑up that gives you 100 Ω differential. I once routed a 28 Gbps lane with a 12 mil mismatch and spent a whole afternoon chasing a flaky eye diagram. Lesson learned: measure twice, route once. ### 3.2 Use proper termination A 100 Ω termination resistor at the receiver end is a must. Some boards also add a series resistor (≈ 30 Ω) near the driver to damp reflections. If you’re using a mezzanine connector, check the connector’s insertion loss – it can eat up a few dB at 28 Gbps. ### 3.3 Power and ground planes Separate the analog (PLL) and digital (logic) supplies. Decoupling caps of 0.1 µF placed within 1 mm of the transceiver pins keep the supply noise low. A solid ground plane under the differential pair acts as a shield and helps maintain the 100 Ω impedance. ## 4. Firmware – Building the Link Layer ### 4.1 Set up the transceiver IP core In the FPGA design tool, instantiate the SERDES IP block and configure: * Line rate = 28 Gbps * Encoding = 64b/66b (or 8b/10b if your protocol demands it) * Gearbox = 20 : 1 (for 28 Gbps, the parallel width is usually 20 bits) Most tools will auto‑generate a “reset controller” and a “status monitor.” Keep those signals exposed in your top‑level design – they are lifesavers when you need to debug. ### 4.2 Implement a simple PRBS generator A Pseudo‑Random Bit Sequence (PRBS) checker is the quickest way to verify link integrity. Insert a PRBS31 generator on the TX side and a PRBS31 checker on the RX side. When the error count drops to zero, you know the physical link is sound. ### 4.3 Add a basic protocol wrapper If you’re just testing the lane, a simple “raw data” mode works. For real applications, wrap the data in a lightweight protocol – for example, a 64‑bit header with a CRC. This gives you early visibility into packet loss or corruption without building a full Ethernet stack. ## 5. Bring‑Up and Debug ### 5.1 Eye diagram first Connect a high‑speed oscilloscope or a dedicated SERDES analyzer to the output. Look for a clean eye with at least 0.8 UI (unit interval) opening. When tuning the eye, consider techniques from our article on [optimizing SERDES eye diagrams](/serdesinsights/optimizing-serdes-eye-diagrams-for-56-gbps-fpga-designs) to squeeze out extra margin. ### 5.2 Use the transceiver status registers Most FPGA transceivers expose registers for: * PLL lock status * CDR (Clock Data Recovery) lock * Bit error count Read these registers via your debug interface (JTAG, UART, or a simple memory‑mapped register). A “CDR not locked” flag usually points to a clocking issue, while a high error count suggests signal integrity problems. ### 5.3 Iterate with small changes When you find a problem, change one variable at a time. For example, if the eye is slightly closed, first try adding a series resistor, then re‑measure. If that doesn’t help, tighten the pair length matching, and so on. This disciplined approach saves a lot of time compared to random tweaks. ## 6. Production Considerations ### 6.1 Signal integrity simulation Before you send the board to fab, run a SPICE or HyperLynx simulation of the differential pair. Include the connector model, the driver’s output swing, and the termination. The simulation will highlight any potential bandwidth bottlenecks. ### 6.2 Test‑point design Add a spare connector or a test‑point near the transceiver pins. In production, a quick loop‑back test can verify that the lane still meets the 28 Gbps spec after assembly. ### 6.3 Firmware versioning Keep the SERDES configuration (line rate, encoding, gearbox) in a version‑controlled file. When you need to tweak the lane for a new board revision, you’ll know exactly what changed. ### 6.4 Avoid common pitfalls A lot of time is lost to avoidable mistakes. Our companion piece on [common pitfalls when designing a 28 Gbps SERDES link](/serdesinsights/designing-a-28-gbps-serdes-link-with-fpga-step-by-step-guide-and-common-pitfalls) outlines the most frequent issues and how to sidestep them. Designing a 28 Gbps SERDES link feels a bit like tuning a high‑performance [race car](https://www.amazon.com/s?k=race+car&tag=organizationtip101-20): you need the right engine (FPGA), a clean [fuel line](https://www.amazon.com/s?k=fuel+line&tag=organizationtip101-20) (clock), precise chassis work (PCB layout), and a skilled driver (firmware). Follow the steps above, stay patient, and you’ll see that clean eye diagram you’ve been chasing. The next time a customer asks for “the fastest link you can deliver,” you’ll be ready with a proven, repeatable flow that lives up to the SERDES Insights reputation.