Designing a Low-Jitter Clock Generator for ARM Cortex-M Microcontrollers

A shaky clock can turn a smooth‑running board into a jittery mess, and with the Cortex‑M family being the workhorse of many IoT gadgets, getting the timing right is more important than ever.

Why Jitter Matters

Jitter is the tiny, random variation in the period of a clock signal. In a perfect world every edge would be exactly 10 ns apart for a 100 MHz clock, but in reality you get a few picoseconds or even nanoseconds of wander. For a Cortex‑M that’s usually fine for basic tasks, but when you start using peripherals like SPI, USB, or high‑speed ADCs, that wander can cause missed bits, data corruption, or extra retries. In short, jitter is the silent enemy of reliability.

Picking the Right Oscillator

Crystal vs. MEMS

Most hobbyists start with a simple crystal. They’re cheap, accurate, and easy to find. However, crystals can be sensitive to temperature and mechanical shock, which can add jitter. MEMS oscillators are a newer option. They’re more robust and often come with built‑in jitter filtering, but they cost a bit more.

Frequency Selection

Cortex‑M cores typically like to run at a multiple of 12 MHz or 24 MHz because the PLL inside the chip is designed around those numbers. Pick a crystal or MEMS part that matches one of those base frequencies, then let the PLL multiply up to your target system clock. This keeps the PLL in a comfortable range and reduces phase noise.

Building the Clock Circuit

Keep the Layout Simple

The first rule of clock design is “short and sweet.” Keep the trace from the oscillator to the MCU as short as possible, and keep it away from noisy digital lines. A 30‑mm trace is already long enough to pick up interference.

Use Proper Decoupling

Place a 0.1 µF ceramic capacitor right next to the oscillator pins, and a 10 µF electrolytic a few millimeters away. This combination filters high‑frequency noise and provides bulk energy for the oscillator’s start‑up.

Add a Series Resistor (Optional)

A 33 Ω resistor in series with the crystal can help dampen ringing on the pins, especially if you’re using a through‑hole crystal with long leads. It’s a small price to pay for a cleaner waveform.

Tuning the PLL

The Cortex‑M PLL takes the input clock and multiplies it to the system frequency. Most chips let you set the multiplication factor and a post‑divider. The trick is to choose values that keep the PLL’s internal VCO (voltage‑controlled oscillator) in its sweet spot, usually between 300 MHz and 600 MHz. Staying in that range reduces phase noise, which directly translates to lower jitter at the output.

Example: 8 MHz Crystal to 120 MHz System Clock

Choose an 8 MHz crystal (easy to find, low cost).
Set the PLL multiplier to 15 (8 MHz × 15 = 120 MHz).
Use a post‑divider of 1 (no division).

The VCO runs at 120 MHz, well inside the recommended range, and you get a clean 120 MHz system clock.

Measuring Jitter

You can’t fix what you can’t see. A cheap USB oscilloscope with at least 200 MS/s sampling rate can give you a decent view of the clock edge. Capture a few hundred cycles and use the “jitter” measurement function, or export the data and calculate the standard deviation of the period yourself.

If you don’t have an oscilloscope, a simple frequency counter with a built‑in jitter spec can give you a ballpark figure. Look for a spec of less than 100 ps RMS for most Cortex‑M applications.

Real‑World Anecdote

A few months back I was working on a low‑cost environmental sensor that used a Cortex‑M4 and a cheap 16 MHz crystal. The sensor would sometimes miss UART packets when the temperature spiked. I traced the problem to the crystal’s temperature coefficient causing a few hundred picoseconds of jitter, which the UART’s oversampling couldn’t tolerate. Swapping the crystal for a 16 MHz MEMS part with a tighter temperature spec solved the issue instantly. The lesson? When you’re pushing the edge of a peripheral’s timing budget, the oscillator choice matters more than the MCU’s clock speed.

Putting It All Together

Select a stable oscillator – crystal for low cost, MEMS for robustness.
Match the base frequency to the MCU’s PLL requirements (12 MHz, 24 MHz, etc.).
Lay out the PCB with short traces, proper decoupling, and optional series damping.
Configure the PLL to keep the VCO in its optimal range.
Verify jitter with an oscilloscope or frequency counter before final firmware.

By following these steps you’ll end up with a clock that is both low‑jitter and reliable, letting your Cortex‑M run its tasks without surprise glitches. At Signal Sync we love digging into the nitty‑gritty of timing, because a good clock is the heartbeat of any embedded design.