Build a 4-bit binary counter using only NAND gates

A 4‑bit binary counter may sound like a project for a lab full of fancy ICs, but the truth is you can pull it off with just a handful of NAND gates and a bit of patience. In today’s maker‑friendly world, learning how to do this gives you a deeper feel for how digital systems really work – and it looks great on a breadboard.

Why a NAND‑only counter?

NAND gates are the Swiss army knife of digital logic. Every other gate can be built from them, which means you can create any logic function without buying a separate chip for each. Building a counter this way forces you to think in terms of the most basic building blocks, a habit that pays off when you debug a complex design or need to squeeze a circuit into a tight space.

The basic building blocks

NAND as NOT, AND, OR

A single NAND gate with both inputs tied together acts as a NOT gate (inverter).

A  ──┐
     NAND ──> NOT A
A  ──┘

Two NAND gates can make an AND gate: first NAND the inputs, then NAND the result with itself (invert).

Three NAND gates give you an OR gate: invert each input with a NAND‑as‑NOT, then NAND the two results together.

Flip‑flop from NAND

The heart of any counter is a flip‑flop – a circuit that stores one bit of information. The simplest to build with NANDs is the T (toggle) flip‑flop, which changes state whenever its T input is high on a clock edge.

A T flip‑flop can be made from two NAND‑based SR (set‑reset) latch stages plus a NAND that combines the current output with the T input. The latch itself uses two cross‑coupled NAND gates. When the clock pulse arrives, the T input determines whether the latch toggles or holds.

Designing the 4‑bit counter

Connecting the T‑flip‑flops

A 4‑bit counter needs four T flip‑flops in series. The least‑significant bit (LSB) receives the external clock directly. Each higher‑order flip‑flop gets its clock from the carry output of the stage before it – essentially the point where that stage changes from 1 to 0.

Wiring the carry logic

With NAND gates you can generate the carry signal by AND‑ing the current output (Q) with the clock pulse, then inverting it. Since we already have NAND‑based AND and NOT, the carry becomes a small NAND‑only subcircuit. The result is a clean ripple‑counter: each flip‑flop toggles only when all lower bits have completed a full cycle.

Step‑by‑step wiring guide

Parts list

• 20 NAND gate ICs (74LS00 or equivalent) – you’ll need about 12 gates total, but a few extra never hurt.
• Breadboard and jumper wires
• 5 V power supply
• One push‑button for the clock (debounced with a simple RC network or a Schmitt trigger if you like)
• Four LED + resistor pairs to display the count

Breadboard layout

1. Power rails – connect 5 V and ground to the side rails.
2. Inverters – place pairs of NAND gates with both inputs tied together to create the NOT gates you’ll need for the SR latch and for the carry logic.
3. SR latch – use two cross‑coupled NAND gates for each flip‑flop. Label the outputs Q0‑Q3.
4. T input – tie the T input of every flip‑flop to logic high (1) so each stage always toggles when its clock arrives.
5. Clock distribution – feed the push‑button (through a debouncing RC) into the clock input of the first flip‑flop. The carry output from each stage goes to the clock input of the next stage.
6. LED display – connect each Q output through a current‑limiting resistor to an LED, then to ground. You’ll see the binary count as the LEDs light up.

Testing each stage

Start by verifying a single T flip‑flop. Apply a clock pulse and watch the LED toggle on each press. Once you’re confident it works, add the second stage and check that its LED changes only after the first stage has completed a full 0→1→0 cycle. Continue adding stages until all four are operating. If a stage misbehaves, double‑check the carry NAND network – a missed inversion will freeze the count.

Common pitfalls and how to avoid them

• Floating inputs – any unused NAND input left open will pick up noise and cause erratic behavior. Tie unused inputs to VCC (logic high) or GND as appropriate.
• Clock bounce – a mechanical button can generate multiple rapid edges, making the counter skip numbers. A simple RC debouncer (10 kΩ and 0.1 µF) works well, or you can use a Schmitt trigger inverter if you have one handy.
• Power supply noise – NAND gates draw a modest current, but a noisy supply can cause glitches. Decouple each IC with a 0.1 µF capacitor close to its VCC pin.
• Incorrect wiring of the cross‑coupled latch – the two NAND gates must feed each other’s outputs, not their own. A quick visual check of the breadboard rows saves a lot of debugging time.

Wrap‑up

Building a 4‑bit binary counter with only NAND gates is a rewarding exercise that reinforces the core ideas of digital design. You end up with a compact, educational circuit that you can expand into a 8‑bit counter or use as the timing backbone for a simple game or LED display. The process also reminds us why the NAND gate earned its place as the building block of modern electronics – it can do everything if you give it a little patience and a clear wiring plan.

Happy building, and may your counters always ripple smoothly.